キヤノン(株)【7751】の掲示板 2024/02/17〜2024/03/04

Nanoimprint finds a real semiconductor application.

Micron shared a talk yesterday on how NIL could be used for certain DRAM layers. They set this up by showing a trend where what's called "chop" layers are increasing for DRAM nodes and going below the resolution for immersion lithography. These patterning steps remove the dummy structures from the periphery of the dense memory arrays.

The shapes of the pattern for these layers are often difficult to print for optical lithography due to the nature of the optical system. In addition, the overlay requirements are much more relaxed than for other layers in the stack. Given that the NIL tool may be as much as 5x cheaper than an immersion scanner, this makes for a very good value proposition for Nanoimprint Lithography's debut into the leading-edge semiconductor space.

NIL fits this well because it has:
1) Resolution well below immersion lithography
2) No geometry or shape restrictions
3) Relaxed overlay performance versus a scanner
4) lower-cost tool option